Introduction to Verilog HDL

Introduction to Verilog¶

Verilog is one of the most widely used hardware description languages (HDL) in the world of digital design and verification. It allows engineers to describe, simulate, and synthesize digital circuits — from simple gates to complex ASICs and system-on-chips (SoCs).

Verilog is a Hardware Description Language (HDL) used to model electronic systems.
Unlike a software language such as C or Python, which describes sequential instructions, Verilog describes hardware implementation through standard digital cells.

A Verilog program (often called Verilog code or RTL code) represents the architecture of a hardware circuit — its registers, logic gates, and interconnections. The term RTL (Register Transfer Level) refers to the abstraction level most Verilog designs use.

Verilog is standardized under IEEE Standard 1364, first ratified in 1995, and later enhanced in 2001 and 2005 versions. The SystemVerilog extension (IEEE 1800) was introduced later to add verification and object-oriented capabilities.

Why Use Verilog?¶

The main reason engineers use Verilog is productivity and reliability. It is the most widely used hardware description language. It allows digital circuits to be designed, tested, and refined before fabrication.

Key Benefits¶

1. Simulation before hardware : You can test your design in software to catch logic errors early.
2. Hardware Synthesis : The Verilog code can be translated (synthesized) into logic-gates and flip-flops for FPGA or ASIC implementation.
3. Hierarchical design : Large systems can be broken down into smaller reusable modules.
4. Portability : Works across multiple tools and vendors (Synopsys, Cadence, Xilinx, Intel, ARM, RISC-V etc.).
5. Widely supported : Verilog is an industry standard, taught in most VLSI and digital design courses.

A Brief History of Verilog¶

Verilog was created in 1984 by Phil Moorby and Prabhu Goel at Gateway Design Automation.
Initially, it was a proprietary simulation language used for digital logic simulation.

In 1990, Cadence Design Systems acquired Gateway and made Verilog publicly available, which encouraged widespread adoption.
By 1995, the language was standardized as IEEE 1364-1995. Later versions added features like:

• Verilog-2001 – Introduced generate statements, multidimensional arrays, and named port mapping.
• Verilog-2005 – Cleaned up syntax and deprecated older constructs.
• SystemVerilog (IEEE 1800) – Extended Verilog with verification, OOP, and assertions.

Today, Verilog remains the foundation for digital design, with SystemVerilog built on top of it.

How Verilog Works¶

Verilog describes circuits using modules that represent blocks of hardware.
Each module can contain:

• Ports – inputs, outputs, and bidirectional connections.
• Signals – internal wires and registers.
• Behavioral code – Description of how signals change with time or events.
• Structural code – instances of submodules or gates.

Example: AND Gate using Verilog¶

module and_gate (
    input a,
    input b,
    output y
);
  assign y = a & b;
endmodule

Example: D Flip-Flop using Verilog¶

module dff (
    input clk,
    input d,
    output reg q
);
  always @(posedge clk)
    q <= d;
endmodule

Verilog abstraction levels¶

Verilog can describe hardware at multiple abstraction levels:

1. Behavioral level - Procedural blocks (always, initial) with sequential programming constructs (like if-else, case, loops, and procedural assignments), focusing on what the circuit does over time rather than how it's structurally built.
2. Data-flow level - Concurrent continuous assignments (e.g., the assign statement) that model the flow of data through combinational logic. The logic-gates are derived from it.
3. Gate level - Interconnected network of predefined primitive gates (like and, or, not, xor, etc.) and the instantiation of modules, directly modeling the physical structure of the logic.

Basics¶

Syntax Overview¶

module <name> (port_list);
   // Port declarations
   input  a, b;
   output y;
   // Internal signals
   wire temp;
   // Logic description
   assign y = a & b;
endmodule

Data types¶

Operators¶

Procedural Blocks: always and initial¶

Procedural blocks define behavioral code that executes over time.

initial¶

Runs once at the start of simulation. Anything inside this non-synthesizable, but useful to initialize registers during simulation.

initial begin
  $display("Simulation started");
end

always¶

Runs repeatedly based on a trigger event.

always @(posedge clk)
  q <= d;

Continuous Assignments¶

Continuous assignments use the assign keyword to connect signals.

assign y = a & b;

Testbenches in Verilog¶

A testbench is a special piece of Verilog code used to simulate and verify your design. It provides stimulus (inputs) and checks responses (outputs).

Example test bench¶

module tb_and_gate;
  reg a, b;
  wire y;

  // Instantiate design under test (DUT)
  and_gate dut (.a(a), .b(b), .y(y));

  initial begin
    a = 0; b = 0;
    #10 a = 1; b = 0;
    #10 a = 0; b = 1;
    #10 a = 1; b = 1;
    #10 $finish;
  end
endmodule

Simulation and Synthesis Flow¶

Verilog designs go through two major steps:

Simulation¶

Used to verify that the RTL code behaves as expected. Simulators evaluate event-driven behavior and timing using your testbench.

Synthesis¶

Translates RTL code into a gate-level netlist, mapping your logic to standard cells or FPGA LUTs.

Common constructs in RTL design¶

Here are some of the most frequently used Verilog constructs:

Verilog vs other langauages¶

Real-World Use Cases¶

Verilog is used in almost every digital IC design flow:

• FPGA development (Xilinx Vivado, Intel Quartus)
• ASIC design (Synopsys Design Compiler, Cadence Genus)
• Verification (ModelSim, VCS, NC-Sim)
• Academic and research projects

Common Verilog applications include:

• CPU and GPU design
• Communication interfaces (UART, SPI, I²C)
• Digital filters and control logic
• Mixed-signal systems (when used with Verilog-AMS)