Verilog-A Behavioral Modeling¶

Verilog-A provides a natural syntax for expressing relationships between voltages, currents, and internal variables. This natural way of modeling is called Behavioral modeling.

Verilog-A is the standard behavioral modeling language used in the Cadence Spectre environment. It enables simulation of complex systems without requiring transistor-level implementations. While its syntax resembles digital Verilog RTL, it differs in important ways. The language is easy to learn initially, but achieving proficiency takes experience. Verilog-A is also well suited for modeling novel devices that are not supported by BSIM models.

This modeling begins with the procedural block called the analog block, where equations resemble those found in circuit theory and differential calculus.

The Analog Block¶

The heart of every Verilog-A behavioral modeling is the analog begin ... end block. This is where continuous-time equations and contribution statements are written.

Example

analog begin
    I(p, n) <+ V(p, n) / R;
end

This single line implements Ohm's law:

$$ I = \cfrac{V}{R} $$

The analog block supports:

• algebraic equations
• differential equations
• Laplace-based transfer functions
• nonlinear functions (exp, tanh, limexp)
• time-based functions (ddt, idt, timer, transition)

All analog behavior flows from the analog block.

Initial and final conditions¶

initial_step in verilog-a¶

Initialization in verilog-a is done using @(initial_step)¹:

analog begin
    @(initial_step) begin
        x = 0;
        y = 1.2;
    end
end

It executes once at the start of simulation. It is used for initializing internal state variables, setting initial conditions and precomputations of parameters. There is no separate initial block in Verilog-A unlike Verilog.

final_step in verilog-a¶

In addition to initial_step, there is also final_step in verilog-a, which runs at the end of all the events.

Complete example of initial_step and final_step

module bitErrorRate (in, ref) ;
    input in, ref ;
    electrical in, ref ;
    parameter real period=1, thresh=0.5 ;
    integer bits, errors ;

    analog begin
        @(initial_step) begin // Initializing the internal variables
            bits = 0 ;
            errors = 0 ;
        end
        @(timer(0, period)) begin
            if ((V(in) > thresh) != (V(ref) > thresh))
                errors = errors + 1 ;
            bits = bits + 1 ;
        end
        @(final_step) // Printing the final status of the variables
            $strobe("bit error rate = %f%%", 100.0 * errors / bits ) ;
        end
endmodule

The “<+” Contribution Operator¶

The most essential construct is the contribution operator <+, which injects a voltage or current into the analog network.

Contribution statements implement KCL (Kirchhoff's Current Law) and KVL (Kirchhoff's Voltage Law):

• Current contribution: I(a, b) <+ expression;
• Voltage contribution: V(a, b) <+ expression;

These statements do not assign values (like in programming languages). Instead, they "contribute" currents or voltages to the circuit matrix.

Capacitor¶

I(p, n) <+ C * ddt(V(p, n));

Inductor¶

V(p, n) <+ L * ddt(I(p, n));

Because contribution statements build up the circuit equation system, multiple contributions merge automatically without conflicts.

Math functions¶

Verilog-A provides built-in functions for implement various linear and non-linear memoryless algebric equations. These functions help us model :

• device-like I–V curves
• exponential diode-like behavior
• limiter or saturation models

Power operator¶

In Verilog-A, the power operator is represented by the double asterisk symbol (**). It is used to raise a base to the power of an exponent.

Syntax and Usage

The basic syntax for the power operator is:

result = base ** exponent;

It can be used with both integer and real (floating-point) numbers. For example:

• x**2 calculates x².
• y**0.5 calculates √y.

Alternative to power operator

pow(x,y) can be used as an alternative to x**y.

sqrt() function¶

It used to calculate the square root of a real-valued expression. Frequently used in noise modeling (for calculating RMS values) and in the geometric calculations of device dimensions.

`include "disciplines.vams"

module voltage_sqrt(in, out);
    input in;
    output out;
    electrical in, out;

    analog begin
        // Safety check: ensure input is not negative to avoid NaN/Errors
        if (V(in) >= 0) begin
            V(out) <+ sqrt(V(in));
        end else begin
            V(out) <+ 0; // Or handle as an error/limiting case
        end
    end
endmodule

limexp(x) and exp(x)¶

In Verilog-A, the exp() function calculates the natural exponential e^x for a given real-valued argument.

I(a, c) <+ is * (exp(V(a, c) / (n * $vt)) - 1);

Verilog-A provides the limexp() function, which is a "limited exponential." It behaves like exp() but prevents the simulator from crashing if the voltage gets too high (avoiding numerical overflow).

I(a, c) <+ is * (limexp(V(a, c) / (n * $vt)) - 1);

ln(x) and log(x)¶

Logarithmic functions are often used to model compression, sensors (like pH or decibel meters), or to invert exponential relationships.

• ln(x) : Natural logarithm (Base-e)
• log(x): Base-10 logarithm

// Modeling a sensor where output voltage is proportional to decibels
V(out) <+ 20 * log(V(in) / v_ref);

abs(x)¶

The abs() function in Verilog-A returns the absolute value of a real number, effectively stripping its sign to provide the non-negative magnitude. It is commonly used in behavioral modeling to calculate distances or to ensure that parameters like power dissipation remain positive regardless of current direction.

Comprehensive list of Math functions : Verilog-A Built-in math functions

Differential Equations for Analog Systems¶

While algebraic equations capture instantaneous relationships, analog systems with memory require differential equations. These define how system variables evolve over time and are central to modeling:

• filters
• oscillators
• sensors
• feedback systems
• Inductors and Capacitors

In Verilog-A, differential equations are expressed using operators such as:

ddt() – Time Derivative¶

The derivative operator ddt(x) returns the time derivative dx/dt. For example, modeling a capacitor:

I(p,n) <+ C * ddt(V(p,n));

This matches the fundamental capacitor equation:
$$i=CdV/dt$$

idt() – Time Integral¶

The integral operator idt(x, initial) integrates a signal over time and is useful for modeling accumulators or custom states.

Example for an integrator:

V(out) <+ gain * idt(V(in), 0);

The second argument in the idt function is intial condition.

Higher-Order Systems¶

Second and higher-order systems can be expressed using multiple derivatives or internal state variables. For example, a mass‑spring‑damper system:

F(node) <+ m * ddt(ddt(x)) + b * ddt(x) + k * x;

This allows engineers to model mechanical or electro‑mechanical systems as easily as electrical circuits.

State Variables¶

For complex models, internal real variables track the system’s evolving behavior:

real x;
analog begin
    x = idt(f - k*x, 0);
    V(out) <+ x;
end

This technique allows designers to build behavioral models of:

• PLL loops
• ΔΣ modulators
• controlled oscillators
• sensor front‑ends

Differential equation modeling is the backbone of high‑accuracy analog abstraction.

Modeling Ideal and Non‑Ideal Components¶

One of the first steps in Verilog-A learning is modeling basic passive components. This builds intuition and teaches how physical laws are translated into code.

Ideal Resistor¶

The simplest ideal component is a resistor:

`include "discipline.vams"
module resistor(p, n);
    inout p, n;
    electrical p, n;
    parameter real R = 1k;

    analog begin
        I(p,n) <+ V(p,n) / R;
    end
endmodule

This directly implements Ohm’s law.

Ideal Capacitor¶

I(p,n) <+ C * ddt(V(p,n));

Ideal Inductor¶

V(p,n) <+ L * ddt(I(p,n));

These models are compact and mathematically exact.

Modeling Non‑Ideal Components¶

Real physical components include imperfections that affect performance. Verilog-A allows you to incorporate these effects easily.

Non‑Ideal Resistor¶

A non‑ideal resistor may include:

• temperature dependence
• parasitic capacitance
• noise contributions

Example:

I(p,n) <+ V(p,n)/R * (1 + alpha*(temperature - 300));
I(p,n) <+ Cpar * ddt(V(p,n));

Non‑Ideal Capacitor (ESR + ESL)¶

I(p,n) <+ C * ddt(V(p,n));
V(p,n) <+ ESR * I(p,n) + ESL * ddt(I(p,n));

Non‑Ideal Inductor (winding resistance + core loss)¶

V(p,n) <+ L * ddt(I(p,n)) + Rw * I(p,n);

These enhancements create much more realistic simulation results in:

• RF circuits
• sensor interfaces
• switched-capacitor systems
• power electronics

Noise Modeling¶

Verilog-A supports noise sources using built‑in functions like:

I(p,n) <+ white_noise(4 * k * temperature / R, "thermal");

This enables high‑accuracy modeling for:

• low‑noise amplifiers
• ADC reference systems
• oscillators and PLLs
• sensor front‑ends

Comparison of behavioral modeling between Verilog and Verilog-A¶

More about noise-modeling in : Verilog A noise modeling