Verilog-A Convergence and Simulation control

Introduction¶

Analog simulators such as SPICE, Spectre, and Verilog-A and AMS engines solve nonlinear differential equations iteratively. If models introduce discontinuities, rapid transitions, or unstable derivatives, the simulation can fail to converge.

Three foundational aspects that every Verilog-A model developer must understand:

1. Limiting functions — controlling internal variables to prevent unrealistic jumps
2. Avoiding discontinuities — preserving derivative continuity for Newton-Raphson stability
3. Improving simulator convergence — best practices for stable compact and behavioral models

Mastering these concepts ensures robust models that behave well across DC, AC, and transient simulations.

Importance of convergence¶

Analog solvers rely on iterative algorithms, primarily:

• Newton-Raphson for nonlinear DC and transient solutions
• Linearization around operating points for AC analysis

If a model produces sharp discontinuities or undefined derivatives, convergence algorithms may:

• Fail to find a solution
• Take extremely long to simulate
• Produce unrealistic waveforms
• Interrupt transient analysis unexpectedly

Thus, convergence optimization is a core requirement in Verilog-A modeling.

Limiting Functions in Verilog-A¶

Limiting functions are used to prevent internal variables — especially exponential or division expressions — from growing too quickly or becoming numerically unstable.

Common Limiting Functions¶

Example: Replacing Exponential with limexp()¶

Raw exponential:

I(p,n) <+ Is * (exp(V(p,n)/Vt) - 1);
````

Improved numerical stability:

```verilog
I(p,n) <+ Is * (limexp(V(p,n)/Vt) - 1);

Limiting Node Voltage Growth¶

Vds_limited = limit(Vds, -3, 3);

This prevents extreme values that break SPICE solvers.

Transition-Based Logic¶

When switching states, avoid instantaneous jumps:

ctrl_smooth = transition(ctrl_signal, 0, 1e-3, 1e-3);

Smooth transitions improve transient performance dramatically.

Avoiding Discontinuities¶

Discontinuities cause:

• Derivative spikes → Newton solver divergence
• Slow convergence due to repeated stepping back
• Unpredictable behavior during AC linearization

The most common source is conditional logic (if/else).

Hard Discontinuity Example¶

if (V(in) > 0)
    out = 1;
else
    out = -1;

This has zero slope, which breaks Newton-Raphson.

Recommended Smooth Alternative¶

out = tanh(V(in)/Vscale);

Smooth hyperbolic tangent creates continuous behavior.

Techniques to Replace Hard Boundaries¶

Use Soft Nonlinear Functions¶

• smoothclip()
• smoothstep()
• tanh() based sigmoid curves

These maintain derivative continuity, essential for convergence.

Improving Simulator Convergence¶

Simulation success is influenced by modeling practices that support:

• Valid startup conditions
• Continuous charge conservation
• Realistic physical response

Provide Proper DC References¶

Never leave nodes floating:

Floating behavior:

I(out) <+ C * ddt(V(out));

I(out) <+ C * ddt(V(out)) + Gmin * V(out);

A small conductance (e.g., Gmin = 1e-12) avoids infinite impedance nodes.

Avoid Pure Integrators¶

Pure integrators destabilize DC operating point:

V(out) <+ idt(input);

Solution: Provide initial condition and leakage:

V(out) <+ idt(input, Vinit) + Gmin*V(out);

Smooth Nonlinear Derivatives¶

Replace:

sqrt(max(x, 0))

with:

sqrt(x*x + eps)

where eps is a tiny smoothing constant.

Prevent Parameter Extremes¶

Validate physical limits:

parameter real L = 1u from (0.1u:10u);

This prevents NaN values from illegal inputs.

Checking Model Compatibility¶

Model should support all simulation types:

Run corner and Monte-Carlo checks to verify robust modeling.

Testing for Convergence Robustness¶

Recommended tests:

• Sweep independent inputs across full operating range
• Apply small current-pulse perturbations to check stability
• Run very slow and very fast transients
• Validate response with random initial conditions

A well-designed model must remain stable under all simulations.

Best Practices Cheat Sheet¶