Verilog-A Device Modeling Basics

Semiconductor Device Equations (MOSFET & BJT)¶

The foundation of every device model lies in semiconductor physics. Even compact models used in simulators are derived from physical equations related to carrier transport, charge dynamics, and electrostatic relationships. Verilog-A provides a structured way to translate these equations into simulatable models.

MOSFET Device Equations¶

A MOSFET’s behavior can be divided into cutoff, linear (triode), and saturation regions. These regions are determined by the gate-source voltage and drain-source voltage with respect to the threshold voltage.

Threshold Voltage¶

The threshold voltage defines channel inversion:

$$V_{TH} = V_{FB} + 2\phi_F + \frac{\sqrt{2\varepsilon_s q N_A \cdot 2\phi_F}}{C_{ox}}$$

This expression depends on doping concentration, oxide thickness, and material properties.

Drain Current Equations¶

For long-channel MOSFETs, the classical current equations are:

Cutoff region:
$$I_D = 0$$

Linear region:
$$I_D = \mu C_{ox} \frac{W}{L}[(V_{GS}-V_{TH})V_{DS} - \frac{V_{DS}^2}{2}]$$

Saturation region:
$$I_D = \frac{1}{2}\mu C_{ox} \frac{W}{L}(V_{GS}-V_{TH})^2(1+\lambda V_{DS})$$

In Verilog-A:

if (Vgs <= Vth)
    Id = 0;
else if (Vds < (Vgs-Vth))
    Id = mu*Cox*(W/L)*((Vgs-Vth)*Vds - 0.5*Vds*Vds);
else
    Id = 0.5*mu*Cox*(W/L)*pow(Vgs-Vth,2)*(1 + lambda*Vds);

I(drain, source) <+ Id;

Short-channel effects such as velocity saturation, DIBL, and channel-length modulation is omitted for simplicity.

Using if-else statements introduce discontinuities in the device model which leads to convergence problems in simulations. Smoothening functions (smoothstep(), transition(), tanh()) are used instead.

BJT Device Equations¶

BJT operation is based on minority carrier injection. The Ebers–Moll conduction principle gives:

$$I_C=I_S(e^{V_{BE}/V_T}-1)$$

Verilog-A implementation:

Ic = Is * (exp(Vbe/Vt) - 1);
I(collector, emitter) <+ Ic;

Gummel-Poon enhancements model:

• Base narrowing
• Charge storage dynamics
• High-level injection

Example charge storage implementation:

Qd = tauF * Ic;
I(base, emitter) <+ ddt(Qd);

Compact Modeling Techniques¶

Compact models provide a balance between physical accuracy and simulation efficiency. They are the standard for SPICE simulation because they must remain:

• Physically meaningful across large operating ranges

• Continuous and differentiable for solver convergence

• Lightweight enough to simulate large circuits

Region Blending & Smoothing¶

To avoid convergence failure, compact models replace if-else decisions with smooth transitions:

• smoothstep()
• transition()
• Hyperbolic tangent functions

Example :

Id = mix(Id_lin, Id_sat, smoothstep(Vds - Vdsat));

This provides numeric stability.

Charge-Based Modeling¶

Charge-based modeling is essential for AC and transient accuracy:

I(gate, source) <+ ddt(Qgs);
I(gate, drain) <+ ddt(Qgd);

This ensures correct dynamic behavior instead of approximating capacitances.

Surface-Potential Formulations¶

Modern nodes (<100 nm) require surface-potential-based approaches rather than threshold-voltage-based ones due to:

• Strong short-channel effects

• Mobility degradation

• Quantum confinement

Widely used models include:

These models are delivered as Verilog-A source for industry simulators.

Multi-Physics Enhancements¶

Compact models also include:

• Self-heating ($temperature)

• Gate leakage

• RF parasitics

• Aging and reliability impacts

These ensure realistic behavior under extreme conditions.

Parameterization & Scaling¶

Parameterization allows one Verilog-A model to represent various device geometries and process conditions without rewriting the equations.

Parameter support¶

Example of geometry parameters:

parameter real W = 1u from (0:inf);
parameter real L = 0.1u from (0:inf);

These can be overridden per-device in SPICE netlists.

Scaling with Dimensions¶

Key geometric factors modeled include:

• Resistance scales with L/W
• Threshold voltage shifts with channel length
• Capacitance depends on fringing fields

Example mobility scaling:

mu_eff = mu0 / (1 + theta * (Vgs - Vth));

Process corners¶

Models must represent statistical manufacturing variations:

Often controlled by pre-processor

`ifdef FAST
    Vth = Vth_fast;
`endif

Temperature dependence¶

Verilog-A supports temperature-dependence modeling:

Vt = k*$temperature/q;
Is = Is0 * pow($temperature/Tnom, 3);

Variability and Monte-carlo¶

Random variation modeling enables yield analysis:

deltaVth = $rdist_normal(seed, 0, sigmaVth);

This allows engineers to evaluate circuit robustness.