Introduction
Junction Field-Effect Transistors are 3 terminal devices. The control terminal is called Gate and the channel is present between Source and Drain. These are always depletion-mode devices because the channel is already present when VGS=0 and it requires negative VGS to decrease the current.
Since the Gate-Source junction is reversed biased, the Gate terminal doesn’t draw any significant current. A weak voltage source (which has a higher output resistance) can also drive a JFET. So, it is a voltage-controlled device. That is why sometimes to achieve very high input impedance in bipolar amplifiers, JFET is used at the input stage.
It is important that the Gate-Source junction is never forward biased because if it is then a high amount of current will flow from the Gate terminal which can result in undesirable behaviour.
JFET is a unipolar-transistor, in which the current is controlled and transported by carriers of one polarity (majority) only. In N-channel JFET electrons are the majority charge carriers. It is unlike BJTs (which is bipolar device) where both types of charge carriers (electrons or holes) participate in conduction. In NPN transistor, the base current is due to hole current and collector current is due to electrons.
Construction of JFET
A simplified diagram is shown above. We can notice that the channel is sandwiched between opposite polarity doped gate.
Actual construction of an N-JFET. Here also we can observe that the N-channel is sandwiched between P-type gates.
Principle of operation
JFET is a transistor where the width of the conduction channel between Source-Drain is controlled by the depletion region of reverse biased Gate-Source junction. This modulation of conduction channel’s width results in transistor behaviour.
Schematic symbols
I-V characteristics
Ohmic region (VDS < VGS - Vp)
Here in this region, the depletion region is not wide enough to pinch-off the channel region.
$$I_{DS} = I_{DSS}\left[2\left(1-\cfrac{V_{GS}}{V_p}\right)\left(\cfrac{V_{DS}}{-V_p}\right)-\left(\cfrac{V_{DS}}{V_p}\right)^2\right]$$
For small VDS, the JFET act as voltage controlled resistor. The resistance across drain and source is set by VGS.
Saturation region/pinch-off (VDS > VGS - Vp)
In (current)saturation region, the channel pinch-off is achieved by VDS. If VDS > VGS-Vp, the channel is pinched-off from charge carriers near the drain and VDS loses control over IDS. So, the IDS saturates to a value decided by VGS only.
$$I_{DS} = I_{DSS}\left(1-\cfrac{V_{GS}}{V_p}\right)^2$$
There is still some weak control left of VDS to IDS. That is due to channel length modulation. Due to which the IDS increases with VDS. It can be captured by using the following equation,
$$I_{DS} = I_{DSS}\left(1-\cfrac{V_{GS}}{V_p}\right)^2\left(1+\lambda{}V_{DS}\right)$$
Cut-off (VGS < Vp)
In the cut-off region, the channel pinch-off is achieved by VGS. If VGS < Vp, the channel is completely devoid of charge carriers and IDS becomes zero.
$$I_{DS} = 0$$
Breakdown region
Due to very high electric field in the depletion region due to high VGS, avalanche multiplication happens. Due to this the current increases rapidly with VDS as shown in in this figure. If the current is not controlled through a series resistor, the device may heat up quickly and get destroyed.
Biasing of JFET
