What is an NMOS transistor ?
NMOS stands for N-channel metal-oxide-semiconductor. The structure of an NMOS transistor consists of three main regions: an n-type source, an n-type drain, and a p-type substrate. The current flow through a N-type channel formed between source and drain in the P-type body. The Gate is separated from the body using a thin oxide SiO2.
Operation of NMOS transistor
NMOS transistors operate by applying a voltage to the gate terminal, which controls the current flow between the source and drain terminals. When a positive voltage is applied to the gate terminal relative to the source, it creates an electric field that attracts electrons (negative charge carriers) from the P-type bulk region toward the gate. This electric field forms a conducting N-type channel (“inversion layer”) between the source and drain (on the surface of bulk), allowing current to flow.
In NMOS transistors, most carriers are electrons, and the current flow occurs when the gate voltage is higher than the source voltage (in a common configuration known as enhancement mode). The transistor is turned off when the gate voltage is lower than the source voltage.
Contruction of NMOS transistor
An NMOS transistor consists of three terminals: the source (S), the drain (D), and the gate (G). The source and drain are heavily doped regions of semiconductor material (typically silicon), while the gate is separated from the channel by a thin insulating layer of silicon dioxide (SiO2). The gate is made of a conductive material such as metal.
Substrate
The substrate is typically p-type semiconductor material (e.g., silicon). The connection to the substrate is made using p+ doping called bulk (B). There is no separate well required as in PMOS structure.
Source and drain region
On the surface of the substrate, there are two heavily doped n-type regions known as the source and drain. These regions are created by introducing impurities (e.g., phosphorus or arsenic) into the substrate through a process called diffusion.
Channel region
A thin layer of n-type carriers is located near the surface between the source and drain region in the p-type substrate when the gate voltage applied is less than the source voltage. Since the carrier type changes from p-type to n-type near the surface of the substrate, this process is called “inversion”.
Gate (Control terminal)
Above the channel region is a thin insulating layer (usually silicon dioxide) followed by a metal gate electrode. The gate controls the conductivity of the channel by applying a voltage. If the voltage at the gate is higher than the threshold voltage with respect to source terminal, the NMOS becomes conductive. Otherwise it is turned off.
NMOS transistor I-V characteristics
Current-voltage relationship in triode region
Total charge present in the channel (assuming long channel) during linear region (when there is no pinch-off),
$$Q_N=W\cdot{}\cfrac{q_N(y=0)+q_N(y=L)}{2}\cdot{}L$$
$$I_{DS}=\cfrac{Q_N}{T}$$
‘T’ is the time it takes the total charge to cross the channel length,
$$T=\cfrac{L}{v_d}=\cfrac{L}{\mu{}_oE}$$
L is the channel length, vd is the velocity of the charge carriers, μo is the mobility of charge carriers, E is the electric field in the channel
$$\implies{}I_{DS}=W\cfrac{\mu{}_oQ_NE}{L}$$
$$E=-\cfrac{V_{DS}}{L}$$
$$\implies{}I_{DS}=-W\cfrac{\mu{}_oQ_NV_{DS}}{L^2}$$
$$q_N(y=0)=-(V_{GS}-V_{TH})C_{ox}$$
$$q_N(y=L)=-(V_{GD}-V_{TH})C_{ox}$$
$$\implies{}I_{DS}=\cfrac{\mu{}_oC_{ox}W(V_{GS}+V_{GD}-2V_{TH})V_{DS}}{2L}$$
$$\implies{}I_{DS}=\cfrac{\mu{}_oC_{ox}W(V_{GS}+V_{GS}-V_{DS}-2V_{TH})V_{DS}}{2L}$$
$$\implies{}I_{DS}=\mu{}_oC_{ox}\cfrac{W}{L}\left(V_{GS}-V_{TH}-\cfrac{V_{DS}}{2}\right)V_{DS}$$
The above equation represents the drain-source current of MOSFET in the linear region.
Current-voltage relationship in pinch off region
Current-voltage relationship in cutoff/subthreshold/weak-inversion region
According to the basic model, the transistor is turned off if VGS is less than VT. A more accurate model considers the effect of thermal energy on the electrons present in each energy band level, similar to a diode/BJT. This results in very less current flowing from the channel called sub-threshold current/leakage.
The subthreshold leakage becomes a very significant number when there are billions of transistors like in a microprocessor. The leakage happens even if the gates are turned off.
The current-voltage relationship is similar to a diode:
$$I_{DS}\simeq{}I_{D0}\exp{\left(\cfrac{V_{GS}-V_{TH}}{\eta{}V_T}\right)}$$
Summary
- NMOS is built with an N-type source and drain and a P-type substrate.
- NMOS, carriers are electrons.
- When a high voltage is applied to the gate, NMOS will conduct.
- When a low voltage is applied in the gate, NMOS will not conduct.