N-Channel MOSFET (NMOS)¶

NMOS stands for N-channel metal-oxide-semiconductor. The structure of an NMOS transistor consists of three main regions: an n-type source, an n-type drain, and a p-type substrate. The current flow through a N-type channel formed between source and drain in the P-type body. The Gate is separated from the body using a thin oxide SiO₂.

NMOS symbol¶

There are minimum three terminals in a NMOS : Gate, Source and Drain. Most of the symbols assume Source and body shorted. Otherwise there is another terminal called Body. In integrated circuit designs, the p-type body is usually the universal substrate (unless specified).

Symbol with the arrow at the body is popular in power electronics and discrete designs. Symbol with arrow at the source is popular in signal chain and IC design domain. The circle at the gate is popular in digital electronics.

The body arrow always points from the P-type material to the N-type material. In a N-channel device, the channel is N-type and the substrate (body) is P-type, so the arrow points inwards (towards the channel). If the arrow is shown at the source terminal, it indicates the direction of current flow when the device in turned on. In N-channel MOSFET, the source terminal arrow points outward. Arrow is never shown at the drain terminal as drain terminal does not control the current flow.

In many discrete MOSFET symbols, an internal parasitic diode is shown pointing from the drain to the source for P-channel devices.

Contruction of NMOS transistor¶

An NMOS transistor consists of three terminals: the source (S), the drain (D), and the gate (G). The source and drain are heavily doped regions of semiconductor material (typically silicon), while the gate is separated from the channel by a thin insulating layer of silicon dioxide (SiO₂). The gate is made of a conductive material such as metal.

Substrate¶

The substrate is typically p-type semiconductor material (e.g., silicon). The connection to the substrate is made using p+ doping called bulk (B). There is no separate well required as in PMOS structure.

Source and drain region¶

On the surface of the substrate, there are two heavily doped n-type regions known as the source and drain. These regions are created by introducing impurities (e.g., phosphorus or arsenic) into the substrate through a process called diffusion.

Channel region¶

A thin layer of n-type carriers is located near the surface between the source and drain region in the p-type substrate when the gate voltage applied is less than the source voltage. Since the carrier type changes from p-type to n-type near the surface of the substrate, this process is called "inversion".

Gate (Control terminal)¶

Above the channel region is a thin insulating layer (usually silicon dioxide) followed by a metal gate electrode. The gate controls the conductivity of the channel by applying a voltage. If the voltage at the gate is higher than the threshold voltage with respect to source terminal, the NMOS becomes conductive. Otherwise it is turned off.

Operation of NMOS transistor¶

NMOS transistors operate by applying a voltage to the gate terminal, which controls the current flow between the source and drain terminals. When a positive voltage is applied to the gate terminal relative to the source, it creates an electric field that attracts electrons (negative charge carriers) from the P-type bulk region toward the gate. This electric field forms a conducting N-type channel (“inversion layer”) between the source and drain (on the surface of bulk), allowing current to flow.

In NMOS transistors, most carriers are electrons, and the current flow occurs when the gate voltage is higher than the source voltage (in a common configuration known as enhancement mode). The transistor is turned off when the gate voltage is lower than the source voltage.

Importance of channel inversion¶

Without electron inversion layer underneath the gate oxide (V_GS=0), there is always a reverse biased diode blocking current flow when a V_DS is applied. With channel inversion, there is a parallel path through inverted channel which conducts current.

NMOS current-voltage relationship¶

NMOS transistor in the triode region behaves as a voltage-controlled resistor (similar derivation as done in PMOS). The relation of drain-source current with gate-source and drain-source voltage for a enhancement mode NMOS is given below:

Triode region¶

$$I_{DS}=\mu{}_oC_{ox}\cfrac{W}{L}\left(V_{GS}-V_{TH}-\cfrac{V_{DS}}{2}\right)V_{DS}$$

The above equation represents the drain-source current of MOSFET in the linear region.

Pinch-off region¶

When V_DS > V_GS – V_TH, the inversion charge at the drain disappears (becomes zero). The drain current becomes constant. The current no longer depends on the V_DS. The current saturates to value when V_DS = V_GS - V_TH.

So, substituting V_DS = V_GS - V_TH in :

$$I_{DS}=\mu{}_oC_{ox}\cfrac{W}{L}\left(V_{GS}-V_{TH}-\cfrac{V_{DS}}{2}\right)V_{DS}$$

We get current relationship for pinch-off region :

$$I_{DS}=\cfrac{\mu{}_oC_{ox}}{2}\cfrac{W}{L}\left(V_{GS}-V_{TH}\right)^2$$

In Measurement, we observe that the current slightly increases with an increase in VDS, so we add a fudge factor:

$$I_{DS}=\cfrac{\mu{}_oC_{ox}}{2}\cfrac{W}{L}\left(V_{GS}-V_{TH}\right)^2\left(1+\lambda{}V_{DS}\right)$$

Subthreshold or weak-inversion region¶

According to the basic model, the transistor is turned off if V_GS is less than V_T. A more accurate model considers the effect of thermal energy on the electrons present in each energy band level, similar to a diode/BJT. This results in very less current flowing from the channel called sub-threshold current/leakage.

The subthreshold leakage becomes a very significant number when there are billions of transistors like in a microprocessor. The leakage happens even if the gates are turned off.

The current-voltage relationship is similar to a diode:

$$I_{DS}\simeq{}I_{D0}\exp{\left(\cfrac{V_{GS}-V_{TH}}{\eta{}V_T}\right)}$$

Enhancement and Depletion mode N-channel MOSFET¶

Enhancement Mode is represented by a dashed line between the drain and source, indicating the channel is not naturally formed and broken. Depletion Mode PMOS is represented by a solid line, indicating a built-in channel exists.

Enhancement mode N-channel MOSFET¶

The Enhancement Mode NMOS (Normally-OFF) is a three-terminal device consisting of the Source (S), Gate (G), and Drain (D) terminals. It does not have a pre-existing channel between source and drain. When a positive gate-to-source voltage (V_GS) exceeding the threshold magnitude is applied, a channel is formed. Once formed, applying a positive drain-to-source voltage initiates conduction.

Case 1 (V_GS ≤ 0) Since there is no channel formed, even with a postive V_DS there is no drain current I_DS.

Case 2 (V_GS > 0) Electrons from the p-type substrate and n-type source and drain, are attracted toward the gate terminal, creating the N-channel near the surface below the gate oxide. The surface act as a bridge between source and drain terminal, causing ( I_DS ) to flow when a positive V_DS is applied.

Depletion mode N-channel MOSFET¶

A N-channel depletion MOSFET (Normally-ON) is a three-terminal device similar to a N-channel enhancement MOSFET. The key distinction is that a N-type channel is already present (diffused during manufacturing) at zero bias; otherwise, the structure and terminals remain the same.

A N-channel depletion MOSFET is structurally analogous to an P-channel depletion device; the primary difference lies in the polarity of the applied terminal voltages and resulting current directions. Because the channel is pre-formed, unlike in an enhancement-type MOSFET, a drain current flows even when the gate-to-source voltage is zero.

Case 1 (V_GS=0) When a positive V_DS is applied, electrons from the pre-formed N-channel drift toward the drain terminal, initiating drain current I_D. As the magnitude of V_DS increases with V_GS=0, the drain current saturates, where I_D becomes constant and does not vary with V_DS and reaches maximum called I_DSS.

Case 2 (V_GS<0) Holes from the P-type substrate are attracted toward the negatively biased gate and recombine with electrons in the N-channel, reducing the available electrons concentration. As the gate voltage reduces, recombination intensifies, further depleting the channel and lowering ( I_D ). Eventually, the drain current becomes zero. The gate voltage at which ( I_D = 0 ) is defined as the pinch-off voltage ( V_P ). The pinch of voltage of Depletion NMOS is negative.

Case 3 (V_GS>0) Electrons are attracted from P-type body (and also from N-type drain and source) towards the gate terminal, increasing the electron concentration in the N-channel. This enhancement of channel charge raises the drain current, causing ( I_D ) to exceed the zero-bias saturation current.

Threshold Voltage¶

There are four physical components of the threshold voltage:

• Work function difference between gate and channel (depends on metal or polysilicon gate): φ_GC

• Gate voltage to invert surface potential: -2φ_F

• Gate voltage to offset depletion region charge: Q_B/C_ox

• Gate voltage to offset fixed charges in the gate oxide and oxide-channel interface: Q_ox/C_ox

$$C_{ox}=\cfrac{\epsilon{}}{t_{ox}}$$

No substrate bias¶

If V_SB = 0 (no substrate/body bias):

$$V_{T0}=\phi{}_{GC}-2\phi{}_F-\cfrac{Q_{B0}}{C_{ox}}-\cfrac{Q_{ox}}{C_{ox}}$$

Non-zero substrate bias¶

$$V_{T}=V_{T0}+\gamma{}\left(\sqrt{|-2\phi{}_F+V_{SB}|}-\sqrt{|2\phi{}_F|}\right)$$

γ is called body effect (substrate-bias) coefficient:

$$\gamma{}=\cfrac{\sqrt{2qN_A\epsilon{}_{Si}}}{C_{ox}}$$

Threshold voltage increases as V_SB increases.

NMOS capacitor¶

Channel formation results in the creation of a NMOS capacitor structure. The gate terminal functions as one conductive plate, while the induced channel region serves as the opposing plate, together forming a parallel-plate capacitor across the gate oxide insulator.

This capacitor is highly nonlinear. The capacitance value changes a lot with gate-bulk voltage. Since, this MOS capacitance is so dependent on gate voltage, it is used as variable capacitance in Voltage controlled oscillator.

Accumulation region¶

A negative gate-to-body voltage attracts holes from the p-type body toward the region beneath the gate oxide. The polysilicon gate acts as one plate of the gate capacitance, while the accumulated holes layer forms the opposing plate. This holes layer is electrically accessible through the body terminal. Access via the source and drain terminals is not possible because body p–n junctions remain reverse biased. The capacitance is maximum and equal to the oxide capacitance (C_ox).

Depletion region¶

A slight positive gate-to-body voltage attracts electrons toward the region beneath the gate oxide. These electrons recombine with the holes and form neutral region. The body near the surface is neutral now and depleted of any charge carriers. Due to this neutral region, the distance between the equivalent parallel-plate capacitor increases. The capacitance is minimum at this point.

Inversion region¶

A strong positive gate-to-body voltage attracts electrons from n-type source and drain toward the region beneath the gate oxide. The polysilicon gate acts as one plate of the gate capacitance, while the inverted electron layer forms the opposing plate. This charge layer is electrically accessible through the source and drain terminal. Access via the body terminal is not possible because the p–n junction is reverse biased. The capacitance is maximum again and equal to the oxide capacitance (C_ox).

At higher frequency of operation, the inversion of channel takes time. Therefore, the effective capacitance at higher frequency is low as shown above.

If the temperature is increased, the thermal carrier generation rate increases. Therefore, higher instrinsic carrier concentration. Minority carrier responds to HF CV, approaches LF CV at very high temperature.

NMOS vs PMOS differences¶

Key differences between a NMOS and a PMOS are tabulated below :

Summary¶

1. NMOS is built with an N-type source and drain and a P-type substrate.
2. NMOS, carriers are electrons.
3. When a high voltage is applied to the gate, NMOS will conduct.
4. When a low voltage is applied in the gate, NMOS will not conduct.